Spacers are key elements in modern metal-oxide-semiconductor (MOS) devices. They provide several key functions. Besides insulating gate electrodes and source/drain regions, they are also used as implant masks for implanting source and drain regions and forming silicide regions.
Typically, spacers are formed by blanket depositing a dielectric layer after the formation of gate electrodes, forming and patterning a photo resist on the dielectric layer, and etching undesired portions of the dielectric layer. Remaining portions of the dielectric layer, typically including vertical portions on the sidewalls of the gate electrodes and possibly small horizontal portions adjacent the vertical portions, become spacers.
Since significant portions of spacers are vertical, conventional single layer spacers suffer non-uniformity problems. Also, over-hang takes place at the top corners of the spacers. These problems are further worsened by the scaling of the integrated circuits. Higher performance requirements in small-scaled integrated circuits demand thinner spacers, and any non-uniformity and/or over-hang significantly affects the profiles of the spacers, and hence the uniformity of MOS devices on a semiconductor chip.
To solve the above-discussed problems, composite spacers have been developed. One of the most commonly used composite spacers has an oxide-nitride-oxide (ONO) structure. FIGS. 1A through 1F illustrate a conventional formation process of a MOS device having spacers with an ONO structure. In FIG. 1A, a stacked layer comprising an oxide layer 4, a nitride layer 6 and an oxide layer 8 is formed, followed by the deposition of a polysilicon layer 10 over gate electrode 2. FIG. 1B illustrates the patterning of polysilicon layer 10. In FIG. 1C, the remaining polysilicon portions act as mask layers, and the unmasked portions of the oxide layer 8, nitride layer 6, and oxide layer 4 are removed. Referring to FIG. 1D, remaining portions of polysilicon layer 10 and oxide layer 8 are removed, and an oxide layer 14 is formed. A mask (not shown) is then formed, and unmasked portions of the oxide layer 14 are removed, forming spacer portions 16, as shown in FIG. 1E.
Spacers having an ONO structure typically have a lower aspect ratio than single-layer structures; thus subsequent gap filling processes are easier.
MOS devices formed using the previously discussed steps generally exhibit good performance when fabricated using 90 nm technology or beyond. However, when MOS devices are scaled down to 65 nm and below, they begin to suffer drawbacks. Referring to FIG. 1F, MOS devices formed at 65 nm and below have very shallow junctions. Thus the distance D1 between silicide regions 17 and the respective junction borders is small. This results in current crowding effects, and thus the drive current of the resulting MOS device is adversely affected. Additionally, source/drain leakage current, which is symbolized by arrow 19, becomes significant due to the short leakage current path.
Another problem associated with the conventional ONO structure is that the stress applied by stressed etch stop layer 18 is reduced. Typically, the stress applied to the channel region of the MOS device is inversely related to a distance D2 between the stressed etch stop layer 18 and the channel region of the MOS device. A large spacer portion 16 increases the distance D2, and thus decreases the stress applied by the stressed etch stop layer 18.
What is needed, therefore, is a new spacer scheme eliminating the above-discussed problems while at the same time preserving the advantageous features of the composite spacers.